This invention relates to integrated circuit memory devices, and, more particularly, to a method and apparatus for writing data to memory devices in a manner that expedites testing of memory devices and increases testing flexibility.
Integrated circuits are extensively tested both during and after production and, in some cases, routinely during use after they have been installed in products. For example, memory devices, such as dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d), are tested during production at the wafer level and after packaging, and they are also routinely tested each time a computer system using the DRAMs executes a power up routine when power is initially applied to the computer system. DRAMs are generally tested by writing known data to each location in the memory and then reading data from each memory location to determine if the read data matches the written data. As the capacity of DRAMs and other memory devices continues to increase, the time required to write and then read data from all memory locations continues to increase, even though memory access times continue to decrease.
Various proposals have been made to decrease the time required to test memory devices, such as DRAMs. The time required to write known data to memory devices has been reduced by such approaches as simultaneously writing the same data to each column of each array in the memory device one row at a time. However, some types of testing require that the word lines be kept at a fixed positive voltage for an extended period of time, such as tens of milliseconds. When there are thousands of word lines in one memory device, this testing takes long periods of time since only one word line in each bank of the memory device may be accessed at a time.
Other approaches for reducing testing time include internal circuitry for transferring data from each column of one row to the next row without requiring the memory to be addressed. These approaches have reduced the time required to write known data or a known pattern of data to the memory array. However, when the initial or xe2x80x9cseedxe2x80x9d row to which data are written is defective, this approach to speeding of testing fails.
Additionally, it is very difficult to assess some error margins. In testing one type of error margin, known as xe2x80x9cwriteback marginxe2x80x9d, it is difficult to measure slew rates at which circuitry involved in writing new data to memory cells limits a maximum clock frequency at which the memory device may continue to operate reliably. Since several different portions of the memory device may limit the maximum clock frequency, a series of simple xe2x80x9cgo-no goxe2x80x9d tests at increasing clock frequencies will not provide insight into which mechanism is limiting the maximum clock frequency.
A new memory device design may be empirically found to be susceptible to certain defects that are most readily and efficiently identified through testing using one or more combinations of rows that could not be anticipated when the memory device was designed. Accordingly, only having a capability to invoke tests using combinations of rows chosen from a limited number of pre-programmed combinations is less than optimal.
In the prior art approaches to writing the same data to multiple rows, the rows are often activated at the same time. As a result, large currents are induced in the memory device, sometimes causing signals to be coupled into unintended memory locations and providing the appearance of memory device failure when the memory device may be capable of normal operation.
There is therefore a need to be able to write data to a memory device, while reducing testing time and increasing testing flexibility, that can be implemented on integrated circuits having memory arrays.
In accordance with one aspect of the present invention, a test circuit for a memory device having at least one array of memory cells arranged in rows and columns selectively operates in either a normal mode or a test mode. When operating in the normal mode, the test circuit couples one row of the array to one active word line driver circuit. When operating in the test mode, the test circuit maintains local phase driving signals in an active state over multiple consecutive row activate commands, allowing multiple rows of the memory device to be accessed at the same time in a programmable fashion.
As a result, when tests of a memory cell or other memory device structure involve holding a memory cell or a word line in a specific state or at a specific voltage for an extended period of time, multiple word lines may be sequentially addressed and then tested together. This greatly reduces testing time.
Additionally, by sequentially turning on individual rows, the currents charging the word lines are spread out over time, substantially reducing switching noise that can cause interference with the proper operation of other portions of the memory device. This is useful in a variety of stress tests where multiple rows are activated, such as half-rows high, all rows high and other tests where a groups of rows are tested together.
Additionally, in another aspect of the present invention, the tester may use software control to program any multiple row activation test pattern as desired after the memory devices have been fabricated. This permits the tester to change testing sequences to resolve fabrication problems or to provide for other specialized test needs that develop after the memory device has been designed.
Further, according to another aspect of the present invention, a tester is able to compensate for problems where a first row, known as a xe2x80x9cseedxe2x80x9d row, is programmed with data that are then propagated from one memory cell to another through portions of the memory device before being read external to the memory device. When the seed row is defective, test software can automatically select a different row as the seed row or can rewrite data to the seed row.